A Non-Resonant Self-Synchronizing Inductively Coupled 0.18-μm CMOS Power Receiver and Charger

While the functionality of emerging wireless microsensors, cellular phones, and biomedical implants, to name a few, is on the rise, their dimensions continue to shrink. This is unfortunate because smaller batteries exhaust quicker. Not surprisingly, recharging batteries wirelessly is becoming increasingly popular today. Still, small pickup coils cannot harness much, so induced EMF voltages vEMF.S are low. Modern receivers can resonate these low input voltages to rectifiable levels, but only with a finely tuned capacitor that resonates at megahertz when on chip and at kilohertz when off chip. In other words, resonant rectifiers are sensitive to frequency and dissipate considerable switching power when integrated on chip. Unluckily, excluding the resonant capacitor requires a control signal that synchronizes switching events to the transmitter's operating frequency. The 0.18-μm CMOS prototype presented here derives this synchronizing signal from the coupled vEMF.S by counting the number of pulses of a higherfrequency clock across a half cycle during a calibration phase and using that number to forecast half-cycle crossings. This way, the prototyped IC switches every half cycle to draw up to 557 μW from 46.6–585-mVPK signals with 38%–84% efficiency across 1.0–5.0 cm. List of keywords: Inductive power transmission, contactless charging, wireless power transfer, inductively coupled power, low-threshold rectifier, switched-inductor receiver. I. INDUCTIVELY POWERED MICROSYSTEMS Modern wireless microsystems incorporate sensors, analog and digital processors, and radiofrequency transceivers to satisfy the functional demands of emerging wireless sensor networks [1] and biomedical implants [2]. Unfortunately, the power needed to sense, transmit, receive, and process signals still outpaces power reductions won by the state of the art [3], so microsensors still require more power and energy than tiny batteries can supply [4]. In other words, either the operational life of these devices is short or their functionality is low. Luckily, coupling inductive power wirelessly can supply sufficient power to operate a microsensor [5]−[9] and replenish its onboard battery [10]−[12]. This means that a microsystem, like the one in Fig. 1, can operate on its own between recharge cycles, and as a result, enjoy the benefits of extended operational life. Volumetric constraints also limit the size of the pickup coil. This means the receiver captures a small fraction of the magnetic flux available and produces a correspondingly low electromotive-force (EMF) voltage vEMF.S [13]. This low EMF voltage is the reason why state-ofthe-art rectifiers use resonance to boost voltages to rectifiable levels [14]−[17]. When using a tuned capacitor for this purpose, however, the circuit is more sensitive to frequency. And when on chip, this frequency and its related switching power losses are high. The non-resonant receiver presented here excludes this capacitor and its shortcomings [18]–[19], and derives a synchronizing signal from its incoming signal to orchestrate switching events. To comprehend the benefits and limitations of this technology, Section II describes how resonant and nonresonant power receivers operate. Section III then discusses how the prototyped non-resonant system generates its synchronizing signal and Section IV quantifies how much power it transfers. Sections V and VI describe the IC implementation of the prototype and results measured. In the end, Section VII draws relevant conclusions. II. THE STATE OF THE ART A. Resonant Receivers Bridge-based resonant receivers use a resonating capacitor CR like Fig. 2 shows to boost low input voltages to rectifiable levels [14]−[17]. This way, when the resonant frequency fLC of CR and the pickup coil's inductance LS matches the frequency of the transmitted signal fO, CR receives and returns energy from and to LS in alternating quarter cycles. As a result, the magnitude of CR's voltage |vC| grows across time until vC's positive and negative half cycles in Fig. 3 reaches two diodes above the receiving battery CBAT: 2vD + vBAT. Once this happens, CR stores enough energy to raise vC to 2vD + vBAT within a half cycle, so the diodes conduct all incoming positive and negative half-cycle charge from LS into CBAT. To reduce the voltage dropped across the diodes to millivolts, state-of-the-art implementations configure synchronous MOSFET switches to operate like diodes [21]–[23]. One drawback to this approach is that output power drops drastically when fO deviates from fLC [20]. Tuning fLC to fO by adjusting CR dynamically with a slow feedback loop can overcome this deficiency [24]. But since 200–500-pF capacitors typically resonate with LS at 7– 14 MHz [21]–[23], receivers with CR on chip operate at high frequency. This means that the gate-drive energy lost to charging and discharging the gates of diode-emulating MOSFETs can be substantial at 7–14 MHz, when CR is on chip, especially when considering tiny coils generate little power. Raising CR to nanofarads reduces this frequency and its related losses, but only at the expense of an off-chip capacitor and additional board space. Still, this technology is popular because it does not require a synchronizing signal and it transfers power even when the battery is empty. B. Non-Resonant Receivers The non-resonant receiver in Fig. 4 uses switches SN and SN to short the pickup coil's LS across each half cycle and therefore impress the induced EMF voltage vEMF.S across LS. This way, LS energizes from vEMF.S across each half cycle, which means LS's current iL in Fig. 5 climbs up across vEMF.S's positive half cycle and down across vEMF.S's negative half cycle. SN opens and SP closes near the end of the positive half cycle to steer iL into CBAT. Since a current flowing out of a voltage source constitutes power delivered, synchronizing switching events amounts to ensuring LS's current iL in Figs. 4 and 5 is positive when vEMF.S is positive. So depleting LS and ensuring iL reaches zero at vEMF.S's half-cycle crossing is optimal. SP can open after that [19] or remain closed for another brief period to draw some energy from CBAT [20]. This investment from CBAT, which raises iL in the negative direction, boosts the electromagnetic damping force with which LS draws energy from the magnetic flux present [20]. After this, SN again closes. Similarly, SN opens and SP closes near the end of the negative half cycle to steer iL, which now flows in the opposite direction, into CBAT. SP can open when iL is zero [19] or remain closed for another brief period to draw an energy investment from CBAT [20] that boosts the damping force in LS. Note that, although depleting LS into CBAT requires time (part of τBAT and τBAT in Fig. 5), vEMF.S still supplies charge to LS and CBAT during that time. In other words, the system draws power from vEMF.S across the entire period. The main advantage with this approach is the absence of a resonating capacitor. Without CR, the system is less sensitive to frequency and more compact. And switching losses are lower when fully integrated on chip because the operating frequency fO is low at 125 kHz. Although raising fO is possible, switching gate-drive losses can rise to such an extent that they can overwhelm the little power that a tiny pickup coil generates. The challenge here is synchronizing the switching events to vEMF.S's half-cycle crossings. III. SELF-SYNCHRONIZING NON-RESONANT POWER RECEIVER AND CHARGER Since iL should be positive when vEMF.S is positive, LS should begin draining before vEMF.S transitions between half cycles, as Fig. 5 illustrates, and iL should reach zero at half-cycle crossings. For this, the system must determine the state of vEMF.S, except neither vEMF.S nor the transmitter current iP in Fig. 1 that sets vEMF.S are accessible. The system therefore disconnects LS, which interrupts the power-transfer process, for one and a half periods to sense and program vEMF.S's transition points for subsequent cycles. A. Calibration During calibration, the system senses the beginning of vEMF.S's period TO and counts how many clock pulses appear across vEMF's half cycle. For this, all switches in Fig. 4 except SN, which corresponds to MN in the calibration circuit of Fig. 6, open and MSEN and MSEN connect LS across RSEN, whose impedance is much higher than that of LS at vEMF.S's operating frequency fO. This way, vEMF.S appears across RSEN, as the switching nodes vSW and vSW in Fig. 7 show at 0– 11 and 71–82 μs, and CPSEN in Fig. 6 compares vEMF.S against zero to generate a digital output vSEN that is in phase with vEMF.S. CNTPRED then starts counting fCLK pulses after vSEN's first rising transition and stops after vSEN rises again, at which point register REGPRED stores the count. B. Synchronization At the end of calibration, when vEMF.S enters its positive half cycle, MSEN and MSEN open and CNTPRED resets to start energizing LS from vEMF.S, as Fig. 7 shows at 11 and 82 μs. When the high-if-equal logic in the synchronizer of Fig. 8 determines that CNTPRED reaches nearly half REGPRED's recorded count, CNTPRED resets and vSYNC commands LS to drain into CBAT. After that, LS energizes from vEMF.S across the negative half cycle until CNTPRED again reaches nearly half REGPRED's recorded count. Another half-cycle sequence then begins and the process repeats. Since LS should start draining before the onset of another half cycle to ensure iL is in phase with vEMF.S, the subtractor in Fig. 8 uses Phase Correct, which is an off-chip digital word that is programmable, to subtract 0.5τBAT counts from the first half-cycle count. This means τSHORT is short of 0.5TO by 0.5τBAT, where part of τBAT is the time that LS requires to deplete. As a result, LS empties near vEMF.S's half-cycle crossings, and in the case of Fig. 7, receives investment energy from CBAT immediately after that, as τBAT ends. SP (or SP) in Fig. 4 then opens and SN (or SN) closes to energize LS from vEMF.S alone. Note that LS receives EMF energy as long as iL is nonzero and in phase with vEMF.S, across every half cycle. The purpose of the 0.5-bit correction is to add a bit every other half cycle when the stored count in REGPRED is odd. This way, the 0.5-bit error that results toggles about half of REGPRED's recorded count and never grows. C. Recalibration Since the internal clock fCLK has no relation to vEMF.S's fO, TO's half cycle normally does not fit an exact integer number of fCLK periods. As a result, the system does not drain LS into CBAT exactly at the half-cycle crossings. Whether under or over forecasted, the synchronizer introduces a quantization error τE with every half cycle that compounds over time t to shift vSYNC more and more out of phase with respect to vEMF.S. This is why the compounded time and phase shifts Δτ and Δθ grow with t in Fig. 9, and vSYNC is slow when τE is positive and fast otherwise: Δθ =ωOΔτ = 2πfO τE TO & ' (( ) * ++ t , (1) where ωO is fO in radians per second and t starts when calibration ends. Since the error should not be such that drawing energy from vEMF.S is impracticable, the system recalibrates after CNTRECAL in Fig. 8 counts NPRED number of fO periods, which in the case of Fig. 7 is 7 periods. And since CNTRECAL's vRECAL does not usually align exactly with a half-cycle crossing, vRECAL reconfigures SP in Fig. 4 to drain LS like a diode. This way, LS depletes and does not receive investment energy from CBAT before a recalibration, as iL in Fig. 7 shows at 70 μs when iL falls to zero. IV. POWER TRANSFER A. Uncollected Energy When perfectly in phase, vEMF.S supplies iL at fO to source EMF energy per cycle EEMF.S: * EEMF.S = PEMF.S dt 0 TO ∫ = vEMF.SiL dt 0 TO ∫ , (2) where * refers to perfect in-phase conditions. When out of phase by Δθi, however, vEMF.S supplies a cosine fraction of EEMF.S: EEMF.S(i) = * EEMF.S cos Δθi ( ) . (3) So since vSYNC is more out of phase with vEMF.S after each period, EEMF.S(i) falls after each period to accumulate ETOT in NPER periods between calibration cycles: ETOT = EEMF.S(i) i=1 NPER ∑ = * EEMF.S cos Δθi ( ) i=1 NPER ∑ $ % & ' ( ). (4) In other words, phase shift causes a loss EPH between calibration cycles that is equivalent to EPH = NPER * EEMF.S −ETOT = * EEMF.S NPER − cos Δθi ( ) i=1 NPER ∑ % & ' ( ) * . (5) The EMF energy that the system ceases to draw during a calibration cycle is unfortunately another loss ECAL. Because the calibration cycle begins at the end of a positive half cycle and the system counts across one full cycle starting with a positive half cycle, ECAL is roughly 1.5EEMF.S. Together, unharnessed power in Fig. 10 first falls when the number of periods between calibrations NPER rises because the fraction of uncollected energy ECAL to output energy EEMF.S drops with more energy-collecting periods between calibrations. This trend reverses when a rise in compounded phase-shift losses EPH outpaces reductions in calibration losses ECAL, after which point recalibrations help. This is why EPH and ECAL are at their combined minimum with 7 periods between calibration cycles when fCLK is 5 MHz. And because a higher sampling frequency reduces phase-shift error, EPH does not surpass ECAL until after 16 periods at 14 MHz. B. Consumed Power Since series resistances consume power, the system loses ohmic conduction power PC to SN, SN , SP, SP, and the parasitic series resistance RS of the pickup coil. RS therefore loses S 2 ) RMS ( L R i across entire half cycles, SN and SN's combined resistance 2RN loses ( ) N 2 ) RMS ( SHORT . L R 2 i across τSHORT, SN–SN and SP–SP's RN and RP lose ( ) P N 2 ) RMS ( BAT . L R R i + across τBAT, and SP's diode voltage vD lose iL.DIODE(AVG)vD just before every calibration cycle: ( ) ( ) D ) AVG ( DIODE . L P N 2 ) RMS ( BAT . L N 2 ) RMS ( SHORT . L S 2 ) RMS ( L C v i R R i R 2 i R i P + + + + = . (6) Charging the combined gate capacitances CG of the MOSFETs that comprise the switches also demands energy, so the battery loses gate-drive power PG to charge CG to vBAT every period TO, but only for NPER of every 1.5 + NPER cycles: ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + = ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + ⎟ ⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ = ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + ⎟ ⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ = PER PER O 2 BAT G PER PER O BAT C PER PER O G G N 5 . 1 N f v C N 5 . 1 N T v Q N 5 . 1 N T E P . (7) Similarly, digital circuits and the oscillator draw gate-drive power PDIG more frequently at fCLK from the battery to charge capacitances. COSC in a relaxation oscillator, for example, charges across ΔvOSC and combined parasitic gate capacitance CDIG charges across vBAT to draw ( ) ( ) CLK BAT DIG BAT OSC OSC CLK BAT DIG OSC DIG f v C v v C f v Q Q P + Δ = + = . (8) The controller also requires power PCNTRL to operate. The blocks that operate continuously, for one, dissipate quiescent power PQ. The timer circuit that defines τBAT, however, only engages across two τBAT's of TO, so it consumes 2τBAT/TO of the power PTMR that it draws when it is on. The calibration circuit similarly operates 1.5 of 1.5 + NPER periods, so the system loses a fraction of the calibration power PCLBRT it requires. So overall, PCNTRL is PCNTRL = PQ + PTMR 2τBAT TO " # $$ % & ''+ PCLBRT 1.5 1.5+NPER " # $$ % & '' . (9) But since fCLK is so high, PDIG overwhelms PG and PCNTRL, and PDIG and PC therefore dominate. V. INTEGRATED CIRCUIT The receiver in Fig. 11 uses vSYNC from Fig. 8 to control when to switch the pickup coil and steer LS's charge into the battery CBAT. When enabled by vRECAL, and vSYNC is high, which corresponds to vEMF.S's positive half cycle, MN and MN close to energize LS from vEMF.S, which is why LS's current iL in Fig. 7 rises across 11–14 μs. When vSYNC falls, MN opens, and after comparator CPZVS.P senses vSW surpasses vBAT, MP closes to drain LS into CBAT. MP does not open until after a tunable delay τBAT, across which LS drains and then draws energy from CBAT to lower and reverse iL at 15 μs, which raises LS's damping force to derive more power from vEMF.S [18]−[19]. After MP opens, comparator CPZVS.N closes MN when vSW drops below zero. From this point, LS energizes across vEMF.S's negative half cycle from a negative vEMF.S. When vSYNC rises, just prior to vEMF.S's transition to its positive half cycle, MN opens, and after comparator CPZVS.P senses vSW exceeds vBAT, MP closes to drain LS into CBAT. Like in the positive half cycle, MP does not open until after a tunable delay τBAT, across which LS first drains and then draws energy from CBAT. After, comparator CPZVS.N closes MN when vSW drops below zero to complete the cycle. The sequence then repeats until the system recalibrates. Note that all switching events in Fig. 5 occur when LS's iL is nonzero. So when any of the power switches open, iL automatically raises or lowers vSW or vSW until CPZVS.N, CPZVS.N, CPZVS.P, or CPZVS.P engages a switch. In other words, the comparators close MN, MN, MP, and MP only when their drain–source voltages vDS are nearly zero. This means the MOSFETs do not dissipate I–V-overlap power when vSW and vSW transition, when vDS's are high. A. Zero-Volt Comparators Since CPZVS.P and CPZVS.P compare vSW and vSW with vBAT, PFET MGC2 in Fig. 12a balances MGC1's mirrored gate-coupled counterpart when vSW is at vBAT. But since MMIR3 steers an offset current only when vSW is below vBAT, the output vZVS(H) rises when vSW climbs over vBAT and drops when vSW crosses vBAT on its way down. vZVS(H) rises within 10 ns in Fig. 13 to engage and steer some of iL through MP or MP because iL supplies MGC2 considerably more current than MGC1's 50 nA. MGC2 in Fig. 12b similarly raises vZVS(L) in 10 ns when vSW falls below 0 V. B. EMF Sense Comparator Since the voltage across RSENSE in the calibration circuit of Fig. 6 is low and near 0 V, gatecoupled NMOS pair MGC1 and MGC2 senses when vSW and vSW crisscross. The differential output, whose gain RDIFF1–RDIFF2 limits, then drives an NMOS differential pair with a latching PMOS load mirror that accelerates its response. MHYST sinks an offset current when sensing a positive to negative transition in vEMF.S to keep noise voltage in vEMF.S from producing jitter in the output vDEC. To save power, vCAL and vSEN disconnect and disable the circuit between calibrations. When calibration begins, vCAL rises to establish a bias voltage across MBI3 and connect RSENSE across vSW and vSW. And after all other connections settle and RSENSE consumes all remnant energy in the parasitic capacitances at vSW and vSW, vSEN rises to connect RSENSE across MGC1–MGC2's sources. Then while sensing, CFILT filters high-frequency noise. C. Relaxation Oscillator When vOSC is high in Fig. 15, MCC1 shuts and the latching PMOS load feeds MCC2 two bias currents 2IOSC to discharge COSC with IOSC. vOSC therefore falls across ΔvOSC until ML1–ML2's source–gate voltage vSGL is high enough to engage ML2, after which MCC1's gate rises, ML4 shuts, and MCC2's gate drops. As a result, MCC2 shuts and the latching PMOS load steers 2IOSC into MCC1 to raise vOSC until ML4–ML3's vSGL is again high enough to engage MCC2 and shut MCC1. To swing each terminal across vSGL, vOSC swings 2vSGL in alternating cycles: ΔvOSC = 2vSGL = IOSC COSC TCLK 2 " # $ % & ' . (10) MPP1 and MPP2 then fold and compare the latching currents to generate a digital signal that a high-threshold inverter buffers for gain and sharper clock edges. The oscillating period TCLK that results in the output vCLK establishes the system's clock fCLK to fCLK = 1 TCLK = IOSC 4vSGLCOSC . (11) D. Delay Timer A rise in vTMR starts τBAT and opens MDIS in Fig. 16a to allow MCHG's bias current ICHG to charge CRAMP. When CRAMP's vRAMP rises above VREF's 0.8 V, comparator CPTMR stops τBAT and closes MDIS to reset vRAMP to 0 V. τBAT is therefore the time that ICHG requires to raise vRAMP to VREF: τBAT = CRAMPVREF ICHG = CRAMPVREF 16IEXT , (12) where ICHG is 16IEXT and IEXT and VREF are off chip for testability purposes. This way, τBAT is 70 ns to 1.8 μs when IEXT is 30 nA to 1 μA. The purpose of MPASS is to keep MCHG from conducting and dissipating power when the circuit is off. For this functionality, CPTMR's MNIN––MPIN– and MNIN+–MPIN+ in Fig. 16b compare vRAMP and VREF. MOUT then buffers MNIN––MPIN–'s output to pull CPTMR's vOUT to 0 V quickly. MNIN–– MPIN– sinks a current that is much greater than the circuit's bias current when vRAMP rises above VREF to accelerate the transition. And MHYS sinks an offset current when CPTMR's vOUT is high, after the circuit resets, to establish a hysteresis that reduces output jitter. VI. PROTOTYPE An off-chip 300-nF SMD ceramic capacitor CBAT, off-chip 400-μH 2.6 × 3.5 × 11.7-mm Coilcraft 4513TC pickup coil, and 0.18-μm 510 × 510-μm receiver in Fig. 17 implement the battery and power receiver described in Sections III–V. Although larger pickup coils harness more electromagnetic energy, microsensors cannot accommodate large devices. So under given space constraints, the coil with the least series resistance (i.e., highest quality factor) dissipates the least power. And because transferring energy requires time, the coil's inductance should be low enough to draw the investment energy required from the battery within a half cycle. The pickup coil's equivalent series resistance (ESR) is 9.66 Ω with a quality factor of 29 at 125 kHz, which is the system's operating frequency fO. Transmission distance dC and the coil voltage that dC induces as vEMF.S are adjustable. Since CBAT's 300 nF invests and receives power across discrete 0.5–1.5-μs τBAT intervals in Fig. 5, vBAT incorporates a ripple that, in addition to CBAT's steady-state charge rate, is roughly 5–25 mV when the coils are 10 to 50 mm apart. A. Output Power and Power-Conversion Efficiency Since phase-shift and calibration losses PPS and PCAL subtract power from what vEMF.S can ultimately source as PEMF.S, the system receives PEMF.S – PPS – PCAL as EMF power PEMF.S. Conduction, gate-drive, digital, and quiescent losses in the circuit then subtract power from PEMF.S to leave PEMF.S – PC – PG – PDIG – PQ for CBAT. Power-conversion efficiency ηR is therefore the fraction of PEMF.S that reaches CBAT as PBAT: ηR ≡ PO PIN = PBAT PEMF.S = * PEMF.S − PPS − PCAL ( )− PC − PG − PDIG − PQ * PEMF.S − PPS − PCAL . (13) In this light, with 10 mm of separation dC between the transmitting and receiving coils LP and LS in Fig. 1, the prototyped system draws energy from an induced 585-mVPK vEMF.S to output 560 μW into CBAT as PBAT, as Fig. 18 demonstrates. PBAT is not higher because small coils capture a small fraction of the emanating electromagnetic field and the system loses phase-shift, calibration, conduction, gate-drive, digital, and quiescent power. Of the power drawn from CBAT and LS, the fraction that CBAT gains above what CBAT supplies is 84% at 10 mm, as ηR shows. Since coils harness less energy when farther apart from their emanating source, vEMF.S's peak–peak voltage falls as dC increases, and as a result, so does PBAT. In other words, powertransmission efficiency across the transponder, between the transmitting and receiving coils, falls when dC rises. Receiver efficiency, however, ηR is fairly even at 70%–84% within 30 mm and only down to 67% at 40 mm because ESR and MOS conduction losses PC(ESR) and PC(MOS) dominate and scale with PBAT. Beyond 40 mm, 7.8 μW of quiescent and fOand fCLK-switched losses in PG, PDIG, and PQ, which do not scale with PBAT, dominate, so losses become a greater fraction of PBAT and ηR drops more rapidly. At 50 mm and 66 mVPK of vEMF.S, PBAT and ηR therefore fall to 16 μW and 38%. In this region, PBAT peaks when τBAT is 1.8 μs, and falls when extending τBAT beyond 1.8 μs because investing more energy from CBAT dissipates more power than it generates [19], [25]−[26]. For a given transmitted power, coil separation, and corresponding coupling factor, EMF power PEMF.S delivers maximum output power PO when PO matches ohmic losses in the pickup coil's equivalent series resistance PC(ESR) and conducting MOS switches PC(MOS). In this sense, PO represents the loss of a resistance RO whose value matches that of RS, MN, MN, MP, and MP combined when PO is at its maximum power point. But since PEMF.S also supplies gate-drive, digital, and quiescent losses, PO is PBAT plus all these losses. In Fig. 18, PO is nearly PBAT and matches PC(ESR) and PC(MOS) when the coils are roughly 36 mm apart, so PBAT is as high as possible at this point. This, however, does not mean the transmitter delivers as much power as possible, because reflecting PO, PC(ESR), and PC(MOS) back to the transmitter does not necessarily match conduction losses in the transmitter PC(T). This is why PO climbs with proximity in Fig. 18, because reflected load power in the transmitter rises, but never reaches or surpasses PC(T). In other words, PBAT peaks when losses are low and the transmitter's reflected load matches PC(T), which is when the receiver optimally damps the transmitting source [18]. B. Calibration Frequency Interestingly, reducing the frequency of calibrations, which amounts to counting more vEMF.S periods before recalibrating, raises PBAT, at least initially, as Fig. 19 shows. The reason for this rise in PBAT is the power that the system does not harness during a calibration phase is greater than the power lost to phase-shift error. With more vEMF.S periods between calibrations and a 9.2MHz clock, PBAT eventually flattens and ultimately peaks, past which point phase-shift error dominates. PBAT does not peak with a 14-MHz clock because the programmable range of NPRED, which is the number of vEMF.S periods between calibrations, tops at fifteen, below the threshold above which phase-shift error dominates when fCLK is 14 MHz. PBAT also falls when fCLK rises from 9.2 to 14 MHz. This reduction results because a faster clock consumes more power and a higher sampling rate raises fCLK-switched losses PDIG from 6.2 to 9.9 μW. So in spite of a lower phase-shift error, the system draws more additional power from CBAT at 14 MHz than from vEMF.S to net a lower gain. In other words, power lost to phase-shift error is not as limiting as fCLK-switched losses are, so a slower clock is better. This is why maximum transmission distance dC(MAX) in Fig. 20 peaks at 7 cm when fCLK is 5.25 MHz. Note that dC(MAX) is the distance above which the system cannot output power, so dC(MAX) corresponds to the minimum EMF voltage vEMF.S(MIN) below which PBAT is negative. C. Operating Frequency With a ±20% variation in vEMF.S's operating frequency fO about 125 kHz, the minimum EMF voltage vEMF.S(MIN) rises 33% in Fig. 21. Although the percentage drop seems significant, the resulting 15-mV deviation is small. This is because the synchronizer calibrates and adjusts to fO. For perspective, consider that this adaptability is absent in resonant receivers, where a ±20% mismatch between operating and resonating frequencies results in a 530-mV variation in vEMF.S(MIN) [20]. D. Relative Performance One fundamental advantage of the non-resonant receiver presented here and in [19]–[20] is that it can operate at kilohertz without off-chip capacitors, whereas resonant receivers with up to 514 pF operate at 7–14 MHz [21]–[23], as Table I shows. This means that switching losses are lower and output power is therefore higher when constrained to on-chip integration. Another benefit is frequency insensitivity, because mismatches in [25]–[26] reduces output power PBAT by considerably more than the same variation would here. Another attribute is the ability to invest battery energy, and with it, raise the electrical damping force with which a small pickup coil can draw power. Note that the difference between [19] and [20] is the ability to invest battery energy and between [20] and this work the ability to synchronize to vEMF.S. Ultimately, the drawback here is complexity, because controllers and synchronizers are not necessary in resonant receivers. VII. CONCLUSIONS With 38%–84% power-conversion efficiencies across 1.0–5.0 cm, the 0.18-μm CMOS power receiver prototyped and presented here generates up to 557 μW and operates when vEMF.S is as little as 46.6 mVPK across a coil separation of up to 7.0 cm. The driving advantages of this technology and those of [19]−[20] over their resonant counterparts are low-frequency operation, on-chip integration, and frequency insensitivity. And while [19] and [20] require transmitter information, this system synchronizes to vEMF.S on its own by counting and using the number of clock pulses across a full cycle during a calibration phase to forecast future switching events. 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